CoWoS Explained: TSMC's Advanced Packaging and Why It Bottlenecks AI Chips
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s method for placing a large processor and several stacks of high bandwidth memory side by side on a shared slab of silicon wiring, then mounting that slab on a package substrate. Almost every leading AI accelerator is built this way: Nvidia’s Blackwell and Rubin GPUs, AMD’s Instinct chips, Google’s TPUs and most custom chips designed with Broadcom or Marvell. For the past three years the number of CoWoS wafers TSMC could process each month has capped how many of those chips could ship, more often than the supply of leading-edge wafers did.
This page explains what CoWoS is, how its three variants differ, why AI chips need it, how fast capacity is growing as of October 2026, and what the alternatives are.
What CoWoS is
The name describes the build order.
Chip-on-Wafer (CoW). Finished dies (a GPU, its HBM stacks) are bonded face down onto an interposer wafer. The interposer is a thin layer of very fine wiring that connects the dies to each other. Many interposers sit on one 300mm wafer.
Wafer-on-Substrate (WoS). The interposer wafer is thinned, diced into individual modules and each module is attached to an organic package substrate, the green board-like part that connects to the outside world through solder balls.
The interposer is the point of the whole exercise. A package substrate can route wires tens of microns wide. An interposer, made with chip-fab tools, routes wires around a micron wide. That density lets a GPU talk to eight HBM stacks over thousands of parallel lines at very low energy per bit. Through-silicon vias (TSVs) in a silicon interposer carry power and signals down to the substrate below.
TSMC calls this family “2.5D” packaging: the dies sit side by side rather than stacked on top of one another, but they share a silicon layer that a plain board could never match. True 3D stacking, die on die, is TSMC’s separate SoIC technology, covered below.
CoWoS-S, CoWoS-R and CoWoS-L
TSMC sells three variants. They differ in what the interposer is made of.
| Variant | Interposer | Size today | In volume since | Typical use |
|---|---|---|---|---|
| CoWoS-S | One continuous piece of silicon, with deep trench capacitors built in | Up to about 3.3 times the reticle (about 2,700 mm²) | 2012 | Nvidia A100 and H100, many earlier AI and networking chips |
| CoWoS-R | Redistribution layers (RDL): copper lines in polymer, no silicon | Beyond 3.3 reticles | 2023 | Networking and HPC parts that need size more than density |
| CoWoS-L | RDL interposer with small embedded silicon bridges (local silicon interconnect, LSI) where the densest links are needed | 3.5 reticles and up; 5.5 reticles in volume | 2024 | Nvidia Blackwell, Rubin, large custom accelerators |
The “reticle” is the largest area a lithography scanner can print in one exposure, about 26 × 33 mm (858 mm²). It sets the ceiling for a single die, and it also limits a single silicon interposer, which has to be stitched together from several exposures to grow past it.
CoWoS-S hit a practical wall at around 3.3 reticles. A larger slab of silicon is expensive, yields poorly and wastes wafer area at the edges. CoWoS-L gets around this by using silicon only where it is needed. Small bridge dies handle the dense links, such as the 10 TB/s connection between Blackwell’s two GPU dies or the links to each HBM stack, and cheaper RDL wiring carries the rest. Nvidia’s B200 puts its two reticle-limited dies and eight HBM3E stacks on CoWoS-L.
TSMC says its 5.5-reticle CoWoS is in mass production at 98% yield. Its roadmap, given at its 2026 Technology Symposium, goes to a 14-reticle version holding 20 HBM stacks in 2028, and beyond 14 reticles with up to 24 HBM stacks in 2029.
Why GPUs plus HBM need it
An AI accelerator’s speed is limited by how fast it can feed data from memory into its compute units. That is why HBM exists: stacked DRAM with a 1,024-bit or 2,048-bit interface per stack (see our HBM explainer for how the stacks are built). Eight HBM4 stacks mean more than 16,000 data lines leaving the GPU. Only an interposer-class wiring layer can carry that many signals over short distances.
The second reason is die size. Leading GPUs have hit the reticle limit, so the only way to get more compute in one package is to join two or more reticle-sized dies so that software sees them as one chip. That needs die-to-die links measured in terabytes per second, which again means silicon-class wiring.
Put together, the package is now a big part of the product. TSMC chairman C.C. Wei said in July 2026 that packaging capacity “is so tight that now it limits my customers’ growth.” Packaging is also not cheap; one industry estimate puts CoWoS at roughly $900 to $1,000 per Rubin-class accelerator.
How much capacity there is
TSMC does not publish CoWoS capacity in wafers per month. It has said its CoWoS capacity will grow at a compound annual rate of more than 80% from 2022 to 2027. Everything more precise comes from supply-chain estimates, which are widely reported in Taiwan’s press and broadly agree with each other. The figures below are estimates as of October 2026, not company guidance.
| Point in time | Estimated TSMC CoWoS capacity (wafers per month) |
|---|---|
| End of 2025 | about 70,000 |
| End of 2026 | about 115,000 to 140,000 |
| 2027 | about 170,000 |
| End of 2028 | about 260,000 (analyst projection) |
Outsourced packaging firms add roughly 50,000 to 60,000 wafers per month of related capacity in 2026 on top of TSMC’s own. Nvidia has reportedly reserved more than half of TSMC’s CoWoS output for 2026. Even with this growth, estimates put demand about 20% above supply in mid-2026, narrowing to about 10% by the end of the year.
Most of the new capacity is in southern Taiwan, around Tainan and Chiayi, where TSMC’s AP7 site is being built out in phases. Outside Taiwan, TSMC executive Kevin Zhang said in April 2026 that the company will build CoWoS and 3D-IC capability in Arizona “before 2029.” Amkor is building a $7 billion packaging campus in Peoria, Arizona, with volume production targeted for early 2028 and Apple and Nvidia named as customers.
TSMC lumps advanced packaging, testing and masks into one 10% to 20% slice of its capital spending and does not break packaging out. For how this capex sits inside the broader buildout, see the AI capex value chain.
Alternatives to CoWoS
SoIC (TSMC). System on Integrated Chips is TSMC’s 3D stacking: dies bonded directly face to face with copper-to-copper hybrid bonds and no solder. AMD’s 3D V-Cache and MI300 accelerators use it. TSMC moved from a 9-micron bond pitch to 6 microns in 2025 and plans 4.5 microns with the A14 generation. The two work together: a stacked SoIC chip usually still sits on CoWoS next to its HBM. Our hybrid bonding explainer covers the bonding itself.
EMIB and Foveros (Intel). EMIB (Embedded Multi-die Interconnect Bridge) embeds small silicon bridges directly in the organic substrate, with no interposer layer at all. It has been in volume since 2017 and uses wafer area far more efficiently than a large interposer. EMIB-T adds TSVs to the bridges for better power delivery, supports HBM4, and is rolling out in Intel’s fabs in 2026. Intel says EMIB packages can reach 8 reticles in 2026 and 12 or more by 2028. Foveros is Intel’s 3D stacking line; Foveros Direct uses hybrid bonding. With CoWoS sold out, Intel’s packaging has drawn interest from large chip buyers, with Google, Amazon, Meta, Microsoft and MediaTek all reported as customers or in talks. In July 2026 Wei said Intel’s EMIB-T gives customers helpful flexibility while TSMC’s own packaging is short.
Panel-level packaging (CoPoS). Round wafers waste their edges when cut into big rectangles. TSMC’s CoPoS (Chip-on-Panel-on-Substrate) moves the interposer process to 310 × 310 mm square panels, which fit many more large modules. A pilot line was being equipped in 2026, with volume production planned at Chiayi from around 2028. TSMC is also developing glass substrates; in July 2026 it said glass was about a year from customer production readiness.
OSATs (ASE, SPIL, Amkor). Outsourced semiconductor assembly and test companies have long handled the WoS half of CoWoS for TSMC, attaching finished interposer modules to substrates. In 2026 TSMC began handing out more of the CoW step too, the bonding of dies onto interposers, which it had mostly kept in-house. ASE (which owns SPIL) and Amkor are the main beneficiaries. ASE also sells its own 2.5D and fan-out packaging and is working on CoWoP, a variant that mounts the interposer module on a platform board in place of a conventional package substrate.
System on Wafer (TSMC). At the far end, TSMC’s SoW builds a whole wafer-sized system. A logic-only version has been in production since 2024; a version that integrates HBM is targeted for 2029.
What to watch
Actual capacity against the estimates. If TSMC reaches about 130,000 wafers per month by the end of 2026, the shortfall should narrow. If it does not, accelerator shipments stay rationed into 2027.
The CoW handoff to OSATs. How much of the interposer bonding step ASE and Amkor take on decides how much capacity can be added outside TSMC’s own plants.
EMIB-T’s first big AI design wins. A confirmed high-volume accelerator on Intel packaging would be the first serious crack in CoWoS’s position.
Bigger packages and co-packaged optics. Each step up in reticle count eats more interposer area per chip, so capacity in wafers grows faster than capacity in chips. Optics moving onto the package adds to the load; see co-packaged optics and our primer on optical connectivity in AI infrastructure.
Location. Nearly all CoWoS capacity is in Taiwan today. The Arizona plans from TSMC and Amkor are the first meaningful hedge, and neither reaches volume before 2028.