Hybrid Bonding Explained: How It Works, Why HBM Needs It and Who Supplies the Tools
Hybrid bonding joins two chips by pressing their polished faces together so that copper pads on one fuse directly with copper pads on the other. There is no solder, no bump and no gap. The name comes from the two bonds made at once: the insulating surfaces stick to each other, and the embedded copper pads weld into continuous metal. Because nothing sits between the dies, connections can be packed far closer together than solder allows, and stacks get thinner and cooler.
It is already in volume in image sensors, 3D NAND and AMD processors. The big open question in 2026 is when high bandwidth memory switches to it, and that question decides a lot of equipment orders. This page explains the process, the pitch numbers, where it is used, where HBM adoption stands as of October 2026, and which companies make the tools.
How hybrid bonding works
The conventional way to stack chips uses microbumps: small solder or copper pillars topped with solder, placed on each die and joined by heat and pressure in a thermo-compression (TC) bonder. The gap between dies is then filled with an underfill material. This works, and it is how every HBM stack shipped to date has been built. But each bump needs room around it, the solder adds height, and the underfill layer traps heat.
Hybrid bonding removes the bump. The basic steps:
- Polish. Each surface is planarised with chemical mechanical polishing (CMP) until it is flat to within nanometres. The copper pads are left very slightly recessed below the surrounding oxide or other dielectric.
- Clean and activate. The surfaces are cleaned of particles and treated with plasma, which makes the dielectric surface chemically reactive.
- Bond. The two faces are aligned and brought into contact at room temperature. The dielectric layers stick together on contact.
- Anneal. The bonded pair is heated to a few hundred degrees Celsius. The copper expands more than the surrounding dielectric, closes the tiny recess, and the pads diffuse into each other to form a solid metal joint.
Every part of this is unforgiving. A single particle a fraction of a micron across can leave a void that ruins the bond, so hybrid bonding needs cleanroom conditions closer to a front-end wafer fab than to a traditional packaging line. Placement accuracy has to be far tighter than for bumps. It is also expensive: the bonders cost more than TC tools, and the line needs extra CMP, cleaning and inspection steps.
There are two formats. Wafer-to-wafer (W2W) bonding joins two whole wafers face to face before they are diced. It is fast and reaches the finest pitches, but both wafers must have identically sized dies, and a bad die on either side ruins the pair. Die-to-wafer (D2W) bonding places individually tested dies onto a target wafer one at a time. It is slower but lets you use only known-good dies and mix chips of different sizes and process nodes. Memory arrays and image sensors suit W2W. Chiplets and HBM need D2W.
Pitch: why the numbers matter
Pitch is the centre-to-centre distance between neighbouring connections. Halving it gives four times as many connections in the same area.
| Method | Typical pitch |
|---|---|
| Flip-chip solder bumps on a package substrate | around 100 microns and up |
| Microbumps (HBM, 2.5D chiplets) | about 40 microns historically, down toward 10 microns in the latest HBM |
| Intel Foveros Direct (hybrid) | 9 microns in production, 3 microns on the roadmap |
| TSMC SoIC (hybrid) | 9 microns (2023), 6 microns (2025), 4.5 microns planned with the A14 generation |
| Die-to-wafer research record | about 1 micron |
| Wafer-to-wafer research record | about 200 nanometres |
AMD says its 3D V-Cache, which uses hybrid bonding, gives about 15 times the interconnect density of a microbump-based 3D stack. Finer pitch also means shorter, lower-resistance paths, so energy per bit falls.
Where hybrid bonding is already used
Image sensors. Stacked CMOS image sensors were the first big market. Sony moved its stacked sensors to direct copper-to-copper connections in the 2010s, bonding a pixel wafer to a logic wafer. Most high-end phone camera sensors are now built this way, wafer to wafer.
3D NAND. YMTC’s Xtacking architecture, introduced in 2018, builds the memory array and its control circuitry on separate wafers and hybrid-bonds them together. Kioxia and SanDisk do the same with CBA (CMOS directly Bonded to Array) in their 218-layer BiCS8 generation. Splitting the two lets each wafer use the process that suits it.
Logic. AMD’s 3D V-Cache, first sold in the Ryzen 7 5800X3D in 2022, bonds an extra SRAM cache die to the processor die using TSMC’s SoIC. The second generation moved the cache die underneath the cores so the cores sit closer to the cooler. AMD’s MI300 accelerators stack compute dies on I/O dies the same way. Intel’s Clearwater Forest Xeon server chips, shipping in 2026, use Foveros Direct, and the Fujitsu Monaka processor built with Broadcom uses SoIC. TSMC’s SoIC parts still usually sit on its 2.5D interposer platform; see our CoWoS explainer.
Co-packaged optics. BESI lists co-packaged optics among its hybrid bonding applications, where photonic and electronic dies are stacked. Our page on co-packaged optics covers why switch makers are moving that way.
Why HBM needs it, and when it will get it
An HBM stack is 8 to 16 DRAM dies piled on a base die and joined by thousands of through-silicon vias (the HBM explainer covers the structure). The whole stack has to fit inside a height limit set by JEDEC, the memory standards body. That limit was 720 microns through HBM3E and 775 microns for HBM4. SK hynix has pointed out that 775 microns matches the thickness of a standard logic wafer, which is why the processor and memory need to line up in height.
Every die added to a fixed height means thinner dies and thinner gaps. Microbumps and underfill take up gap space. Hybrid bonding takes none, so at some stack count it becomes the only way to fit everything in. It also helps heat escape; Samsung says hybrid bonding cuts thermal resistance by more than 20% against TC bonding.
For years the industry expected hybrid bonding to arrive with HBM4. It did not. JEDEC’s move to 775 microns let suppliers build 16-high HBM4 with conventional bumps, and they got better at thinning dies and shrinking gaps. All three HBM makers ship HBM4 with conventional stacking: SK hynix with its mass reflow moulded underfill (MR-MUF) process, Samsung and Micron with TC bonding over non-conductive film (TC-NCF).
The position of each maker as of October 2026:
SK hynix said at the Hot Chips conference in August 2026 that hybrid bonding will not be used for HBM4E and that the earliest adoption will be HBM5, and that it will keep using MR-MUF through Nvidia’s Rubin generation. It is still preparing. It has reported finishing validation of a 12-high hybrid-bonded HBM stack, ordered a production-grade Kinex hybrid bonding system from Applied Materials and BESI early in 2026 as a development step, and took delivery of a die-to-wafer hybrid bonding cluster from Hanwha Semitech in April 2026 for evaluation.
Samsung is the most committed. It has said hybrid copper bonding will let it build stacks of 16 layers or more, and has shown it alongside its HBM4E design. It uses BESI equipment for development and has tested hybrid bonders from SEMES, its in-house equipment arm. Samsung is also developing designs that stack DRAM directly on logic.
Micron stacks with TC-NCF and has not given a public date for hybrid bonding in HBM.
Two things could push the date out further. JEDEC has been reviewing a proposal to raise the height limit to about 900 microns from HBM4E onward, with up to 1,000 microns discussed for 20-high HBM5. And memory makers can make dies larger in area instead of stacking more of them. Both reduce the pressure to switch. On current plans the first large hybrid-bonded HBM volumes look like a 2028 to 2030 event, tied to 16-high HBM4E at the earliest and more likely to HBM5.
Who supplies the tools
The tools fall into two groups: die-level bonders, which matter for HBM and chiplets, and wafer-level bonders, which serve image sensors, NAND and some logic.
| Company | Base | Hybrid bonding tools | TC bonding for HBM | Notes |
|---|---|---|---|---|
| BESI | Netherlands | Leading die-to-wafer hybrid bonders; Kinex integrated system with Applied Materials | Yes | 21 hybrid bonding customers by mid-2026; Applied Materials holds about 9% |
| Applied Materials | US | Co-developed Kinex D2W line with BESI; supplies the CMP, deposition and cleaning steps around the bond | No | Largest BESI shareholder since April 2025 |
| Hanmi Semiconductor | South Korea | Developing a hybrid bonder, targeting launch by end of 2027 | Market leader; SK hynix’s main supplier since 2016 | June 2026 order of 44.2 billion won from SK hynix for HBM4 TC bonders |
| Hanwha Semitech | South Korea | SHB2 Nano D2W hybrid bonding cluster, in evaluation at SK hynix | Yes, supplier to SK hynix since 2025 | In a patent dispute with Hanmi |
| ASMPT | Singapore | Hybrid bonding partnership with EV Group | Yes; supplied about half of SK hynix’s HBM4 TC bonders, per late-2025 reports | |
| SEMES | South Korea | Hybrid bonders in testing at Samsung | Samsung’s main TC bonder supplier | Samsung subsidiary |
| EV Group (EVG) | Austria | Wafer-to-wafer hybrid and fusion bonding (BONDSCALE) | No | Long-standing W2W supplier for sensors and memory |
| SUSS MicroTec | Germany | XBS300 W2W, XBC300 Gen2 for D2W and W2W | No | Also sells temporary bonders for thin-wafer handling |
| Tokyo Electron | Japan | Synapse Si permanent bonder for fusion and copper hybrid bonding (image sensors, memory) | No | Synapse V and Z temporary bond and debond tools are used in TSV processing |
A few points that are easy to get wrong. BESI and Applied Materials work together in hybrid bonding: Applied brings the front-end process steps, BESI the bonder. Hanmi is the TC bonding leader but has no hybrid bonder in production. Micron’s HBM TC bonders have historically come from Hanmi and Japan’s Shinkawa, and industry reports say BESI has gained ground there with HBM4. EVG, SUSS and Tokyo Electron are mainly wafer-to-wafer suppliers, which is the format used for image sensors and NAND rather than HBM.
The delay in HBM adoption has helped the TC bonder makers. Hanmi, ASMPT and Hanwha all booked HBM4 TC orders in 2025 and 2026, and Hanmi is building wider TC bonders for larger HBM5 and HBM6 dies. BESI’s hybrid bonding business has grown on logic and other uses in the meantime; its second-quarter 2026 orders were €292.9 million, more than double a year earlier.
Export rules touch this supply chain too, since key tool makers are Dutch and Japanese; see how Dutch and Japanese chip export controls line up with the US.
What to watch
The JEDEC height decision for HBM4E and HBM5. A limit near 900 microns or more keeps conventional stacking alive for another generation. A tighter one forces hybrid bonding sooner.
Samsung’s first hybrid-bonded HBM in production. Samsung has the most to gain from changing the method, since it trailed in the bump-based generations. A qualified hybrid-bonded product at a major GPU customer would push SK hynix and Micron to follow.
Hybrid bonding orders from memory makers. Development tools have shipped to SK hynix and Samsung. Volume orders, dozens of bonders at a time, will be the real signal. BESI told investors in July 2026 that memory customers’ evaluations should play out over the third and fourth quarters.
TSMC’s SoIC pitch roadmap. Logic keeps moving to finer pitches whatever memory does, and AI accelerators that stack cache or compute dies are a growing market of their own. For where packaging sits among the other AI spending tiers, see the AI capex value chain.