For most of the past two years, the scarce input for AI was chips. Increasingly it is electricity. Companies can order GPUs, but they cannot easily get a few hundred megawatts of grid power delivered to a site, and the wait for a new grid connection in many US regions now runs for years. That is why data center deals are announced in gigawatts, why tech companies are signing contracts to restart nuclear plants, and why some sites are building their own gas turbines.

Since October 2022 the United States has required a licence to ship top-end AI accelerators to China. Nvidia’s A100, H100 and later chips, and the servers built around them, can’t legally go to Chinese buyers without one, and for most of that period licences were rarely granted. Demand didn’t go away. A grey market grew to fill it, and since 2025 US prosecutors have brought a run of cases showing how servers worth hundreds of millions of dollars, and in one case billions, were rerouted.

Co-packaged optics (CPO) moves the part that turns electrical signals into light off the front panel of a network switch and onto the same package as the switch chip. Today, almost every fiber link in a data center runs through a pluggable transceiver: a small module, about the size of a pack of gum, that slots into the front of a switch or a server network card. CPO gets rid of most of those modules.

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s method for placing a large processor and several stacks of high bandwidth memory side by side on a shared slab of silicon wiring, then mounting that slab on a package substrate. Almost every leading AI accelerator is built this way: Nvidia’s Blackwell and Rubin GPUs, AMD’s Instinct chips, Google’s TPUs and most custom chips designed with Broadcom or Marvell. For the past three years the number of CoWoS wafers TSMC could process each month has capped how many of those chips could ship, more often than the supply of leading-edge wafers did.

High bandwidth memory (HBM) is DRAM built as a tower. Eight, twelve or sixteen memory dies sit on top of a logic base die, wired together vertically, and the whole stack is placed a few millimetres from a GPU or AI accelerator inside the same package. The reason is bandwidth. One HBM4 stack moves at least 2 terabytes per second, more than three times what a 12-channel DDR5-6400 server socket manages (about 614 GB/s).

Hybrid bonding joins two chips by pressing their polished faces together so that copper pads on one fuse directly with copper pads on the other. There is no solder, no bump and no gap. The name comes from the two bonds made at once: the insulating surfaces stick to each other, and the embedded copper pads weld into continuous metal. Because nothing sits between the dies, connections can be packed far closer together than solder allows, and stacks get thinner and cooler.

This page tracks the main US rules that limit China’s access to advanced chips, AI accelerators and chipmaking equipment. It starts with the October 2022 package and runs to the guidance Washington issued in 2026. Entries are in date order, and each one says what changed and who felt it. Last updated: 15 September 2026. How the controls work The Bureau of Industry and Security (BIS) sits inside the US Commerce Department and writes the Export Administration Regulations (EAR).

AI sovereignty is the capacity of a state to develop, deploy and govern artificial intelligence systems without depending on infrastructure, models or rules controlled by another state. The term entered mainstream policy vocabulary around 2023 and has since been applied to national compute programmes, domestic model development, data residency law and regulatory regimes. It is used loosely, and that looseness matters: the phrase bundles together at least four distinct claims with radically different price tags and success rates.

Nvidia has committed five billion dollars to Safe Superintelligence, the Ilya Sutskever venture that had raised roughly three billion in total and carried a thirty-two billion dollar valuation last year. Nvidia’s own framing emphasizes that the investment comes with GPU access sufficient to raise SSI’s available compute by an order of magnitude. That second clause is the whole story, and the dollar figure obscures it. A single investor writing a check larger than a company’s entire prior funding history is unusual.

Every dollar of AI capital expenditure eventually lands somewhere concrete: a wafer, a switch, a cooling loop, a power purchase agreement, a SaaS seat. Tracking that flow from the hyperscaler earnings call down to the individual equity ticker is the only way to separate durable exposure from sentiment-driven noise. The chain below runs twelve tiers deep rather than the usual eleven, because the packaging layer that sits between memory and networking has become too structurally important to leave folded into a generic equipment bucket.

The case for owning Marvell almost always opens with custom AI chips, and that is the part of the story where Marvell is structurally second. The company and Broadcom are the two names that turn hyperscaler in-house silicon designs into manufacturable chips, the application-specific processors that Amazon, Microsoft, Google and Meta increasingly favor over off-the-shelf GPUs for inference. But Marvell holds roughly 15 percent of that market against Broadcom’s 55 to 60 percent, and Counterpoint expects Broadcom to command about 60 percent of custom AI silicon by 2027.

NVIDIA and Corning Incorporated have announced a multiyear partnership to scale U.S.-based optical connectivity manufacturing for AI infrastructure. The deal commits Corning to a tenfold expansion of its domestic optical connectivity manufacturing capacity, a greater than 50% increase in U.S. fiber production, and the construction of three new facilities across North Carolina and Texas — creating more than 3,000 jobs in the process. To understand why this matters, it helps to understand what optical connectivity actually is and where it sits in the AI infrastructure stack.

A working reference for the vocabulary of modern AI — organized by conceptual layer, not alphabetically. Each definition is written for practitioners and informed generalists: precise enough to cite, plain enough to share. Foundation Layer Large Language Model (LLM) A neural network trained on vast quantities of text to predict and generate language. LLMs learn statistical patterns across billions of documents, enabling them to answer questions, write code, summarize text, and engage in dialogue.