Co-packaged optics (CPO) moves the part that turns electrical signals into light off the front panel of a network switch and onto the same package as the switch chip. Today, almost every fiber link in a data center runs through a pluggable transceiver: a small module, about the size of a pack of gum, that slots into the front of a switch or a server network card. CPO gets rid of most of those modules.

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s method for placing a large processor and several stacks of high bandwidth memory side by side on a shared slab of silicon wiring, then mounting that slab on a package substrate. Almost every leading AI accelerator is built this way: Nvidia’s Blackwell and Rubin GPUs, AMD’s Instinct chips, Google’s TPUs and most custom chips designed with Broadcom or Marvell. For the past three years the number of CoWoS wafers TSMC could process each month has capped how many of those chips could ship, more often than the supply of leading-edge wafers did.

Hybrid bonding joins two chips by pressing their polished faces together so that copper pads on one fuse directly with copper pads on the other. There is no solder, no bump and no gap. The name comes from the two bonds made at once: the insulating surfaces stick to each other, and the embedded copper pads weld into continuous metal. Because nothing sits between the dies, connections can be packed far closer together than solder allows, and stacks get thinner and cooler.