HBM Explained: How High Bandwidth Memory Works, HBM3E vs HBM4, and Who Makes It
High bandwidth memory (HBM) is DRAM built as a tower. Eight, twelve or sixteen memory dies sit on top of a logic base die, wired together vertically, and the whole stack is placed a few millimetres from a GPU or AI accelerator inside the same package. The reason is bandwidth. One HBM4 stack moves at least 2 terabytes per second, more than three times what a 12-channel DDR5-6400 server socket manages (about 614 GB/s). Nvidia’s Blackwell and Rubin GPUs, Google’s TPUs and AMD’s Instinct accelerators all depend on it, and only three companies make it in volume.
This page covers how an HBM stack is built, how the generations compare, where SK hynix, Samsung and Micron stand as of October 2026, and why HBM has pushed up the price of ordinary memory.
How an HBM stack is built
Start with ordinary DRAM dies. For HBM they are thinned to a few tens of microns, far thinner than a standard wafer, so a dozen or more can be stacked within a fixed height. JEDEC, the standards body for memory, capped HBM3E packages at 720 microns and raised the limit to 775 microns for HBM4. That number matters more than it sounds; it decides how many dies fit and which bonding method can be used.
Through-silicon vias (TSVs) carry signals and power up and down the stack. A TSV is a vertical hole etched through a die and filled with copper. Each HBM die has thousands of them, lined up so data can pass straight through the tower to the bottom.
Microbumps join one die to the next. These are tiny solder bumps, bonded either by heating the whole stack at once and filling the gaps with a moulded underfill (SK hynix’s MR-MUF process) or by pressing each layer with heat over a non-conductive film (thermo-compression with NCF, used by Samsung and Micron). The next step, joining dies copper to copper with no solder at all, is covered in our hybrid bonding explainer.
The base die sits at the bottom. It holds the physical interface to the processor, test circuits and power delivery. Through HBM3E the memory makers built base dies on their own DRAM processes. With HBM4 the base die moved to logic processes, because the interface got wider and faster and customers want to put their own logic there. SK hynix buys its HBM4 base dies from TSMC on a 12nm-class process. Samsung makes its own on its 4nm foundry process. Micron built its HBM4 base die in-house and has said TSMC will make the base die for its HBM4E, targeted for 2027. (If those node labels are unfamiliar, see what chip node names actually mean.)
The base die is also where “custom HBM” happens. Micron is working with Nvidia on a custom HBM4E implementation, and Samsung has said custom HBM samples built to customer specifications will follow in 2027.
Why the interface is so wide
A DDR5 memory channel is 64 bits wide (two 32-bit subchannels) and runs fast. HBM goes the other way. HBM2, HBM3 and HBM3E use a 1,024-bit interface per stack; HBM4 doubles it to 2,048 bits. Each pin runs slower than a DDR5 pin, but there are so many of them that total bandwidth is far higher and energy per bit is lower.
The arithmetic is simple: bandwidth per stack equals the number of data pins times the per-pin speed, divided by eight. At the JEDEC baseline of 8 Gbps, an HBM4 stack gives 2,048 × 8 ÷ 8 = 2,048 GB/s.
The catch is the wiring. Two thousand signal lines per stack, times eight stacks, cannot be routed through an ordinary circuit board. They need a silicon interposer or silicon bridges with wires a few microns wide, which is why HBM and advanced packaging rise and fall together. Our CoWoS explainer covers that half of the story.
HBM4 also doubled the number of independent channels per stack, from 16 in HBM3 to 32, so the processor can keep more requests in flight at once.
HBM generations compared
| Generation | Interface | Pin speed | Bandwidth per stack | Stack height | Capacity per stack | First volume use |
|---|---|---|---|---|---|---|
| HBM2E | 1,024-bit | 3.2 to 3.6 Gbps | about 410 to 460 GB/s | 8-high (12-high in spec) | 16 GB typical, 24 GB in spec | 2020 |
| HBM3 | 1,024-bit | 6.4 Gbps | about 819 GB/s | up to 12-high | up to 24 GB | 2022 (Nvidia H100) |
| HBM3E | 1,024-bit | about 8 to 9.8 Gbps | about 1 to 1.2 TB/s | 8-high and 12-high; 16-high sampled | 24 to 36 GB (48 GB at 16-high) | 2024 |
| HBM4 (JEDEC baseline) | 2,048-bit | 8 Gbps | 2 TB/s | 4, 8, 12 or 16-high | up to 64 GB (16 × 32 Gb dies) | 2026 |
| HBM4 (shipping parts) | 2,048-bit | about 10 to 11.7 Gbps | about 2.5 to 3 TB/s | 12-high | 36 GB | 2026 (Nvidia Rubin) |
A few notes on reading the table.
The JEDEC figure is a floor. JEDEC published the HBM4 standard (JESD270-4) in April 2025 with 8 Gbps as the baseline, then Nvidia pushed all three suppliers well past it for Rubin. SK hynix’s HBM4 runs above 10 Gbps. Samsung says its HBM4 runs at a steady 11.7 Gbps and can reach 13 Gbps, which works out to as much as 3.3 TB/s per stack.
Capacity depends on die density as well as stack height. HBM4 allows 24 Gb and 32 Gb dies. Twelve 24 Gb dies make a 36 GB stack, which is what shipped first. A 16-high stack of 32 Gb dies reaches 64 GB.
HBM4E is next. Samsung showed an HBM4E design at 16 Gbps per pin and 4 TB/s per stack in March 2026 and plans to sample it in the second half of 2026. SK hynix shipped HBM4E samples in the first half of 2026. Micron’s HBM4E, with a TSMC-made base die, is aimed at 2027.
At the GPU level the numbers multiply. Nvidia’s Blackwell B300 carries 288 GB of HBM3E. The Rubin GPU uses eight HBM4 stacks for 288 GB. Nvidia announced 22 TB/s of memory bandwidth for it at CES 2026; analyst reports since then suggest shipping parts may land closer to 20 TB/s, which is what eight stacks at 10 Gbps per pin deliver.
Who makes HBM: SK hynix, Samsung and Micron
Three companies supply essentially all HBM used in AI accelerators. The state of play below is as of October 2026. Market shares are by HBM revenue and come from Counterpoint Research’s quarterly estimates.
| Maker | HBM revenue share, Q1 2026 | HBM revenue share, Q2 2026 | HBM4 status |
|---|---|---|---|
| SK hynix | 58% | 50% | Mass shipments since Q2 2026, ramping in H2 |
| Samsung | 21% | 33% | First commercial HBM4 shipments, February 2026 |
| Micron | 21% | 18% | Ramping across a growing customer list |
SK hynix has led the market since the HBM3 generation and is Nvidia’s largest HBM supplier. It finished HBM4 development in September 2025 using its fifth-generation 10nm-class (1b) DRAM, began mass shipments in the second quarter of 2026 and is ramping through the second half. It stacks with MR-MUF and has said it will keep using that method through the Rubin generation. New capacity is coming from its M15X fab, the first phase of its Yongin cluster (cleanroom opening early 2027) and a packaging plant in Indiana targeted for 2028.
Samsung fell behind during HBM3E, when it was slow to qualify with Nvidia; its share dropped to 17% in the second quarter of 2025. It came back with HBM4. Samsung began shipping commercial HBM4 in February 2026, built on its sixth-generation 10nm-class (1c) DRAM with a 4nm base die, and its revenue share jumped to 33% by mid-2026. Most HBM revenue in that quarter still came from HBM3E, so HBM4 volumes in the second half will decide whether the gain holds.
Micron entered at HBM3E and took share quickly, passing Samsung during 2025. In its results on 30 September 2026 Micron said its HBM4 ramp was going well across a growing number of customers. It also said it had agreed most of its calendar 2027 HBM supply with customers at significantly higher prices than in 2026. A new HBM packaging plant in Singapore is due to start output in early 2027.
In June 2026 Nvidia confirmed all three as HBM4 suppliers for its Vera Rubin platform. Supply-chain estimates put SK hynix well ahead in that allocation, with Samsung second.
Chinese buyers are largely cut off from this supply. US rules issued in December 2024 restrict sales of advanced HBM into China; the US chip export controls timeline has the details.
Why HBM squeezes conventional DRAM supply
HBM and the DRAM in laptops, phones and servers come out of the same fabs, on the same wafers. Every wafer a memory maker commits to HBM is a wafer that does not become DDR5 or LPDDR5X. And HBM uses far more wafer per bit.
There are three reasons. HBM dies are larger for the same capacity, because the TSVs and their keep-out zones take up area. Stacking loses some yield, since one bad die or bad bond can scrap a whole stack. And the stack needs a base die that holds no memory at all. Micron has said HBM3E takes about three times the wafer supply of DDR5 for the same number of bits, and that the ratio rises in later generations.
TrendForce estimates HBM took about 18% of total DRAM wafer input at the end of 2025, rising to about 22% by the end of 2026 and about 30% by the end of 2027. Over the same period HBM accounts for only about 9% to 13% of DRAM bits. That gap is the squeeze in one line: a growing share of wafers produces a small share of bits.
The makers chose this. Accelerator customers pay more per bit, sign long contracts and commit early. The result has been tight supply and sharp price rises for conventional DRAM since the second half of 2025, with the effect working its way down to consumer hardware. We traced one example in HBM cannibalization reaching the laptop shelf. Capacity does not flow back quickly either. Shifting a line between products and requalifying parts takes quarters, and new fabs take years.
What to watch
HBM4 speed and yield. Nvidia asked for more than the JEDEC baseline, and suppliers that hit the higher speed bins at good yield will win allocation on Rubin and its successors.
Samsung’s share in the second half of 2026. Its second-quarter jump came before HBM4 volume was visible. If HBM4 shipments hold the 30%-plus level, the market has three real suppliers for the first time.
Custom base dies. As base dies move to TSMC and Samsung logic processes, HBM starts to look like a co-designed part. That pulls foundries into the memory supply chain and ties HBM capacity to advanced packaging capacity even more tightly.
16-high stacks and bonding. Taller stacks within a fixed height are where solder microbumps run out of room. When memory makers switch to hybrid bonding is still an open question, and equipment makers’ order books depend on the answer.
2027 contract pricing. Micron has already locked most of its 2027 HBM output at higher prices. Whether ordinary DRAM prices stay high depends on how much new wafer capacity the three makers add and how much of it goes to HBM. The demand side runs through hyperscaler budgets and where memory sits in the AI capex value chain.