Chip Node Names Decoded: What 3nm, 2nm, Intel 18A and TSMC A16 Actually Mean
A “3nm” chip has no important feature that measures 3 nanometres. Node names stopped describing physical sizes decades ago and now work as generation labels, each one promising a denser, more efficient chip than the last. This page explains where the names came from, how the big foundries’ labels line up, and which numbers actually tell you something.
Last updated: 15 September 2026.
Where the names came from
Through the 1990s a node name roughly matched the length of a transistor’s gate. A 0.35-micron process had gates around 0.35 microns long. As chipmakers found other ways to improve transistors (strained silicon, new gate materials, then 3D FinFET transistors) the gate length stopped shrinking at the old pace. The industry kept the naming cadence anyway, cutting the number by about 30% each generation because that is what a full shrink used to deliver.
By the 2010s the labels had drifted far from anything you could measure. On a modern 3nm-class process the spacing between transistor gates is still in the 40s to 50s of nanometres.
Why Intel renamed its nodes
Intel’s naming was more conservative than its rivals’. Its 10nm process had transistor density close to TSMC’s 7nm. In 2021 Intel renamed its roadmap to line up with how the rest of the industry counted. The enhanced 10nm process became Intel 7, and the next steps became Intel 4 and Intel 3.
Below that Intel switched to angstroms (one angstrom is 0.1 nanometre). Intel 20A was cancelled in 2024 so the company could put its effort into Intel 18A. TSMC followed with A16 and A14, and Samsung plans SF1.4.
Rough equivalence by generation
These groupings are approximate. Each company makes different trade-offs between density, performance and power, and variants within a family can differ a lot.
| Class | TSMC | Samsung | Intel | Others |
|---|---|---|---|---|
| 7nm | N7 (2018) | 7LPP | Intel 7 (formerly 10nm) | SMIC N+2 |
| 5nm | N5, N4 | 5LPE, 4LPP | Intel 4 | SMIC 5nm-class (limited volume) |
| 3nm | N3 family (late 2022) | SF3 (first gate-all-around, 2022) | Intel 3 | |
| 2nm | N2 (volume from late 2025), N2P, N2U (2028) | SF2 (2025), SF2P | Intel 18A (late 2025), 18A-P | Rapidus 2nm (targeting 2027) |
| 1.6nm to 1.4nm | A16 (volume 2027), A14 (2028) | SF1.4 (later in the decade) | Intel 14A | |
| 1.3nm to 1.2nm | A13, A12 (2029) |
What changed at 2nm
Two technologies define the current leading edge.
Gate-all-around transistors
FinFETs wrap the gate around three sides of a vertical fin of silicon. Gate-all-around (GAA) designs stack horizontal ribbons or sheets of silicon and surround each one with the gate on all sides. That gives better control of current leakage at small sizes. Samsung calls its version MBCFET and moved first, at 3nm. TSMC uses nanosheets starting with N2. Intel calls its version RibbonFET and introduced it with 18A.
Backside power delivery
Chips traditionally route power and signals through the same stack of metal layers above the transistors. Moving power lines to the back of the wafer frees room for signals and cuts voltage loss. Intel’s PowerVia arrived with 18A. TSMC’s version, Super Power Rail, arrives with A16, which the company positions for AI and data centre chips. TSMC’s N2 does not use backside power.
That means Intel 18A combined both technologies before TSMC did, while TSMC’s N2 leads on density and manufacturing scale.
Current status of the leading nodes
TSMC N2 entered high-volume production in Taiwan in late 2025. TSMC extended the family with N2P and announced N2U for 2028, a lower-cost update that keeps compatibility with N2P designs.
TSMC A16 adds Super Power Rail to a nanosheet base. It was once expected in 2026. At its 2026 North America Technology Symposium TSMC said volume production would begin in 2027, aligned with customer product plans.
TSMC A14, A13 and A12 follow. A14 is due in 2028. A13, an optical shrink of A14, and A12, which carries backside power forward, are both due in 2029. TSMC says neither needs High-NA EUV lithography.
Intel 18A began volume production in late 2025 and powers the Panther Lake laptop processors (Core Ultra Series 3). Intel is promoting 18A-P, a performance-enhanced version, to outside foundry customers.
Intel 14A is Intel’s next major node and is planned around ASML’s High-NA EUV scanners.
Samsung SF2 went into production in 2025 and is used in the Exynos 2600 smartphone processor. SF2P is the follow-on.
Rapidus, the Japanese government-backed foundry, runs a 2nm pilot line in Hokkaido and targets mass production in 2027.
SMIC produces 7nm-class chips for Huawei without EUV tools and has shipped 5nm-class parts in limited volume. US export controls block its access to EUV scanners.
Numbers that mean more than the name
If you want to compare processes, these metrics carry real information.
Contacted gate pitch (CPP) is the distance between neighbouring transistor gates.
Minimum metal pitch (MMP) is the tightest spacing between wires in the lowest metal layers.
Transistor density is usually quoted in millions of transistors per square millimetre. Foundries calculate it differently. TSMC, for example, quotes a “mixed” density weighted across logic, SRAM and analog blocks, so cross-company density claims should be read carefully.
Performance and power claims are always relative to the company’s own previous node, such as “15% faster at the same power”. They don’t transfer across foundries.
Yield decides cost and supply. Analyst estimates vary widely and companies rarely publish figures, so treat any single yield number with caution.
Quick glossary
Node: a generation of manufacturing process with its own design rules.
Half-node or variant: an improved version of an existing node, such as N2P or 18A-P, usually offering modest gains while keeping design compatibility.
EUV: extreme ultraviolet lithography, used for the finest patterns since the 7nm and 5nm generations. ASML is the only supplier.
High-NA EUV: a newer class of EUV scanner with a higher numerical aperture that can print finer features in a single exposure.
Optical shrink: scaling an existing node’s layout down by a small percentage to gain density without new design rules.
Angstrom: 0.1 nanometre. Used in names like 18A, A16 and A14.