CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s method for placing a large processor and several stacks of high bandwidth memory side by side on a shared slab of silicon wiring, then mounting that slab on a package substrate. Almost every leading AI accelerator is built this way: Nvidia’s Blackwell and Rubin GPUs, AMD’s Instinct chips, Google’s TPUs and most custom chips designed with Broadcom or Marvell. For the past three years the number of CoWoS wafers TSMC could process each month has capped how many of those chips could ship, more often than the supply of leading-edge wafers did.

A “3nm” chip has no important feature that measures 3 nanometres. Node names stopped describing physical sizes decades ago and now work as generation labels, each one promising a denser, more efficient chip than the last. This page explains where the names came from, how the big foundries’ labels line up, and which numbers actually tell you something. Last updated: 15 September 2026. Where the names came from Through the 1990s a node name roughly matched the length of a transistor’s gate.